The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography, or simply lithography. As is well known, lithographic processes can be used to transfer a pattern of a photomask (also referred to herein as a mask or a reticle) to a wafer.
For instance, patterns can be formed from a photo resist layer disposed on the wafer by passing light energy through a photomask having an arrangement to image the desired pattern onto the photo resist layer. As a result, the pattern is transferred to the photo resist layer. In areas where the photo resist is sufficiently exposed and after a development cycle, the photo resist material can become soluble such that it can be removed to selectively expose an underlying layer (e.g., a semiconductor layer, a metal or metal containing layer, a dielectric layer, a hard mask layer, etc.). Portions of the photo resist layer not exposed to a threshold amount of light energy will not be removed and serve to protect the underlying layer during further processing of the wafer (e.g., etching exposed portions of the underlying layer, implanting ions into the wafer, etc.). Thereafter, the remaining portions of the photo resist layer can be removed.
There is a pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged. For example, feature size, line width, and the separation between features and lines are becoming increasingly smaller. For example, nodes with a critical dimension (CD) of about 45 nanometers (nm) to about 65 nm have been proposed. In these sub-micron processes, yield is affected by factors such as mask pattern fidelity, optical proximity effects and photo resist processing. Some of the more prevalent concerns include line end pullback, corner rounding and line-width variations. Contact holes may also have a tendency to bridge and/or shift from a desired location. These concerns are largely dependent on local pattern density and topology.
Optical proximity correction (OPC) has been used to improve image fidelity. In general, current OPC techniques involve executing an OPC software program with accompanying OPC scripts. The OPC program/scripts carry out a computer simulation that takes an initial data set having information relating the desired pattern and manipulates the data set to arrive at a corrected data set in an attempt to compensate for the above-mentioned concerns. The photomask can then be made in accordance with the corrected data set. Briefly, the OPC process can be governed by a set of optical rules (e.g., “rule-based OPC” employing fixed rules for geometric manipulation of the data set), a set of modeling principles (e.g., “model-based OPC” employing predetermined behavior data to drive geometric manipulation of the data set) or a hybrid combination of rule-based OPC and model-based OPC.
Prior to correcting a data set using model-based or hybrid OPC, it may be desirable to verify the operation of the OPC model upon which the OPC routine relies and/or to select one of a plurality of OPC models to be used during the OPC routine. To date, techniques for evaluating OPC models involve intensively manual processes that is time consuming and prone to errors and/or omissions. Briefly, verifying OPC models involve hand checking the layout corrections made to a test pattern to verify that the OPC routine applying the OPC model performs in an expected manner.
Accordingly, there exists a need in the art for an improved methodology of verifying OPC models and for collected data against which the corrections of the OPC models can be compared.